Mixed-signal designs have become ubiquitous with the proliferation of deep submicron (DSM) system-on-chip (SoC) design methodologies. In such designs, maintaining signal integrity and reducing noise have become vexing issues. Switching noise due to large signal swings in the digital part can propagate through the common substrate and corrupt sensitive analog components. In designs that have low resistivity substrates, noise generated in one region of the die may cause the rest of the chip to malfunction. Decreasing feature size lets more devices to be packed on a chip, generating higher overall noise. Smaller devices are also more sensitive to noise because of reduced noise margins. The increasing switching rates and decreasing transition times are also responsible for more transients. Due to these DSM effects, SN analysis (SNA) has become a critical problem in most mixed-signal designs.
Traditionally, SPICE has been the primary tool used by designers for noise analysis. However, it is not feasible to use SPICE on a block having even 100,000 gates. Research work has been done on modeling SN during design phases. Much of this research derives a passive network model that can be simulated with SPICE to yield substrate noise patterns for the entire design for the set of input vectors from a testbench. Each cell in the library is simulated with SPICE for all possible inputs and power supply current and substrate injection currents are extracted. This knowledge is used to do a full-chip analysis. One problem with at least some previous approaches is that they do not consider package inductance and the associated power supply noise, and hence are not very practical. Some previous approaches do not consider the dependency of noise on the load at each gate. In at least one previous approach, a time-series divided parasitic capacitance model is use for time-domain power supply current estimation. Previous approaches are typically input-pattern dependent, i.e., a separate model must be derived for each input pattern. Even for a moderately sized design, the number of models can become very large. This leads to exorbitant run times, making these approaches impractical for a full-chip analysis. Also, there is no guarantee that the maximum noise will be reported, since the worst-case input pattern may not be present in the testbench.